1. Field of the Invention
The present invention relates to a memory device and operating method thereof, and more particularly, to a memory device and operating method thereof having a program/erase state defined differently from that of the conventional.
2. Description of Related Art
Nitride storage non-volatile memory (NVM) is a type of memory that allows many times of data writing, reading and erasing operations. Furthermore, the stored data will be retained even after power to the device is removed. With these advantages, nitride storage NVM has been broadly applied in personal computer and other electronic devices.
A typical nitride storage NVM uses a charge-trapping layer instead of the polysilicon floating gate in a conventional NVM. The charge-trapping layer is fabricated by silicon nitride, for example. The silicon nitride charge-trapping layer is sandwiched between an upper silicon oxide layer and a lower silicon oxide layer, thereby forming an oxide/nitride/oxide (ONO) composite layer. The most common NVM devices are silicon/oxide/nitride/oxide/silicon (SONOS) devices and metal/oxide/nitride/oxide/silicon (MONOS) devices.
The conventional method of determining program or erase state of a memory cell having the ONO structure includes applying an operating voltage on the drain, the gate and the source of the memory cell so that a threshold voltage (or a working voltage) is produced in the charge-trapping layer of the memory cell. Through hot electron or hot hole injection, the memory cell can be erased or programmed.
FIG. 1 is a graph with curves showing the relation between the working voltage Vth and the drain operation voltage VD of a memory cell. As shown in FIG. 1, the curves 101 and 103 represent the relationship between the operating voltage Vth and the drain operation voltage VD for the erase and the program state of a brand-new memory cell. According to FIG. 1, it can be clearly seen that, as the voltage VD at the drain of the memory cell is about 0.24V, the operating voltage difference OM1 between the curves 101 and 103 is about 3V (3.6V−1.6V). Conventionally, this operating voltage difference is used to define the program/erase state of the memory cell. Obviously, when the voltage VD at the drain is about 1.8V, the operating voltage difference OM2 between the curves 101 and 103 is reduced to about 0.46V (1.66V−1.2V) due to the drain inductance barrier lowering (DIBL) effect. Therefore, operating at a higher drain voltage will lead to a retraction of the operating boundary.
In addition, it can be observed from FIG. 1 that when the memory device has completed one cycle of the program/erase operations (set to 1000 operations in FIG. 1), the curve 101 will migrate from its original location up to the curve 105 and the curve 103 will migrate from its original location up to the curve 107. From the standpoint of the drain operation voltage Vd set to 0.24V, the operating boundary (OM3) of the program and erase state has retracted from the original 3V to 2V (4.8V−2.8V). Thus, after the memory device has performed a cycle of operations, a retraction of the operating boundary will occur. Therefore, the memory device is more vulnerable to produce erroneous actions.